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? semiconductor components industries, llc, 2009 july, 2009 ? rev. 0 1 publication order number: ncp1294/d ncp1294 flyback, boost, forward pwm controller the ncp1294 fixed frequency feed forward voltage mode pwm controller contains all of the features necessary to be configured in a flyback, boost or forward topology. this pwm controller has been optimized for high frequency primary side control operation. in addition, this device includes such features as: soft ? start, accurate duty cycle limit control, less than 50 a startup current, over and undervoltage protection, and bidirectional synchronization. the ncp1294 is available in a 16 lead soic narrow surface mount package. features ? 1.0 mhz frequency capability ? fixed frequency voltage mode operation, with feed forward ? thermal shutdown ? undervoltage lock ? out ? accurate programmable max duty cycle limit ? 1.0 a sink/source gate drive ? programmable pulse ? by ? pulse overcurrent protection ? leading edge current sense blanking ? 75 ns shutdown propagation delay ? programmable soft ? start ? undervoltage protection ? overvoltage protection with programmable hysteresis ? bidirectional synchronization ? 25 ns gate rise and fall time (1.0 nf load) ? 3.3 v 3% reference voltage output ? these devices are pb ? free, halogen free/bfr free and are rohs compliant *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. v fb i set 1 ncp1294eg awlyww 16 comp r t c t ss ov lgnd uv v ref ff v cc sync pgnd i sense v c gate pin connections and marking diagram 1 16 http://onsemi.com device package shipping ? ordering information ncp1294edr2g soic ? 16 (pb ? free) 2500 tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specifications brochure, brd8011/d. ncp1294edbr2g tssop ? 16 (pb ? free) soic ? 16 d suffix case 751b 1 16 tssop ? 16 db suffix case 948f ncp1294= specific device code a = assembly location wl, l = wafer lot yy, y = year ww, w = work week g or = pb ? free package ncp 1294 alyw 1 16 2500 tape & reel
ncp1294 http://onsemi.com 2 figure 1. application diagram, 36 v ? 72 v to 5.0 v/5.0 a converter uv ov i set ff gate i sense pgnd v c v ref comp v fb r t c t sync ss lgnd ncp1294 v cc 0.01 f 330 pf 2200 pf 1.0 f 10 k 200 0.22 f fzt688 51 k 11 v v in (36 v to 72 v) 22 f 18 v 160 k 10 0.1 f 470 pf 24.3 k 20.25 k 510 k 4.3 k 13 k 10 62 5.6 k 150 4700 pf 1.0 k 10 k irf634 10 100 pf 10 680 pf d13 v33mla1206a23 mbrb2545ct t3 100:1 t1 4:1 t2 2:5 100 bas21 1.0 f 100 f v out (5.0 v/5.0 a) sgnd 180 1.0 k tl431 0.1 f 5.1 k 2.0 k 2.0 k d11 bas21 moc81025
ncp1294 http://onsemi.com 3 maximum ratings rating value unit operating junction temperature, t j internally limited ? lead temperature soldering: reflow: (smd styles only) (note 1) 230 peak c storage temperature range, t s ? 65 to +150 c esd (human body model) 2.0 kv stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. 60 second maximum above 183 c. maximum ratings pin name pin symbol v max v min i source i sink gate drive output gate 15 v ? 0.3 v 1.0 a peak, 200 ma dc 1.0 a peak, 200 ma dc current sense input i sense 6.0 v ? 0.3 v 1.0 ma 1.0 ma timing resistor/capacitor r t c t 6.0 v ? 0.3 v 1.0 ma 10 ma feed forward ff 6.0 v ? 0.3 v 1.0 ma 25 ma error amp output comp 6.0 v ? 0.3 v 10 ma 20 ma feedback voltage v fb 6.0 v ? 0.3 v 1.0 ma 1.0 ma sync input sync 6.0 v ? 0.3 v 10 ma 10 ma undervoltage uv 6.0 v ? 0.3 v 1.0 ma 1.0 ma overvoltage ov 6.0 v ? 0.3 v 1.0 ma 1.0 ma current set i set 6.0 v ? 0.3 v 1.0 ma 1.0 ma soft ? start ss 6.0 v ? 0.3 v 1.0 ma 10 ma logic section supply v cc 15 v ? 0.3 v 10 ma 50 ma power section supply v c 15 v ? 0.3 v 10 ma 1.0 a peak, 200 ma dc reference voltage v ref 6.0 v ? 0.3 v lnternally limited 10 ma power ground pgnd n/a n/a 1.0 a peak, 200 ma dc n/a logic ground lgnd n/a n/a n/a n/a electrical characteristics ( ? 40 c < t a < 85 c; ? 40 c < t j < 125 c; 3.0 v < v c < 15 v; 4.7 v < v cc < 15 v; r t = 12 k; c t = 390 pf; unless otherwise specified.) characteristic test conditions min typ max unit start/stop voltages start threshold ? 4.4 4.6 4.7 v stop threshold ? 3.2 3.8 4.1 v hysteresis start ? stop 400 850 1400 mv i cc @ startup v cc < uvl start threshold ? 38 75 a supply current i cc operating ? ? 9.5 14 ma i c operating 1.0 nf load on gate ? 12 18 ma i c operating no switching ? 2.0 4.0 ma
ncp1294 http://onsemi.com 4 electrical characteristics ( ? 40 c < t a < 85 c; ? 40 c < t j < 125 c; 3.0 v < v c < 15 v; 4.7 v < v cc < 15 v; r t = 12 k; c t = 390 pf; unless otherwise specified.) characteristic unit max typ min test conditions reference voltage total accuracy 0 ma < i ref < 2.0 ma 3.2 3.3 3.4 v line regulation ? ? 6.0 20 mv load regulation 0 ma < i ref < 2.0 ma ? 6.0 15 mv noise voltage 10 hz < f < 10 khz. note 2 ? 50 ? v op life shift t = 1000 hrs. note 2 ? 4.0 20 mv fault voltage ? 2.8 2.95 3.1 v v ref(ok) voltage ? 2.9 3.05 3.2 v v ref(ok) hysteresis ? 30 100 150 mv current limit ? 2.0 40 100 ma error amp reference voltage v fb = comp 1.234 1.263 1.285 v v fb input current v fb = 1.2 v ? 1.3 2.0 a open loop gain note 2 60 ? ? db unity gain bandwidth note 2 1.5 ? ? mhz comp sink current comp = 1.4 v, v fb = 1.45 v 3.0 12 32 ma comp source current comp = 1.4 v, v fb = 1.15 v 1.0 1.6 2.0 ma comp high voltage v fb = 1.15 v 2.8 3.1 3.4 v comp low voltage v fb = 1.45 v 75 125 300 mv psrr freq = 120 hz. note 2 60 85 ? db ss clamp, v comp ss = 1.4 v, v fb = 0 v, i set = 2.0 v 1.3 1.4 1.5 v comp max clamp note 2 1.7 1.8 1.9 v oscillator frequency accuracy ? 260 273 320 khz voltage stability ? ? 1.0 2.0 % temperature stability ? 40 c < t j < 125 c. (note 2) ? 8.0 ? % max frequency note 2 1.0 ? ? mhz duty cycle ? 80 85 90 % peak voltage note 2 1.94 2.0 2.06 v valley clamp voltage ? 0.9 0.95 1.0 v valley voltage note 2 0.85 1.0 1.15 v discharge current ? 0.85 1.0 1.15 ma synchronization input threshold ? 0.9 1.4 1.8 v output pulse width ? 200 320 450 ns output high voltage 100 a load 2.1 2.5 2.8 v input resistance ? 35 70 140 k sync to drive delay time from sync to gate shutdown 100 140 180 ns output drive current r sync = 1.0 1.0 1.5 2.25 ma 2. guaranteed by design, not 100% tested in production.
ncp1294 http://onsemi.com 5 electrical characteristics ( ? 40 c < t a < 85 c; ? 40 c < t j < 125 c; 3.0 v < v c < 15 v; 4.7 v < v cc < 15 v; r t = 12 k; c t = 390 pf; unless otherwise specified.) characteristic unit max typ min test conditions gate driver high saturation voltage v c ? gate, v c = 10 v, i source = 200 ma ? 1.5 2.0 v low saturation voltage gate ? pgnd, i sink = 200 ma ? 1.2 1.5 v high voltage clamp ? 11 13.5 16 v output current 1.0 nf load. note 3 ? 1.0 1.25 a output uvl leakage gate = 0 v ? 1.0 50 a rise time 1.0 nf load, v c = 20 v, 1.0 v < gate < 9.0 v ? 60 100 ns fall time 1.0 nf load, v c = 20 v, 9.0 v < gate < 1.0 v ? 25 50 ns max gate voltage during uvl/sleep i gate = 500 a 0.4 0.7 1.0 v feed forward (ff) discharge voltage i ff = 2.0 ma ? 0.3 0.7 v discharge current ff = 1.0 v 2.0 16 30 ma ff to gate delay ? 50 75 125 ns overcurrent protection overcurrent threshold i set = 0.5 v, ramp i sense 0.475 0.5 0.525 v i sense to gate delay ? 50 90 125 ns external voltage monitors overvoltage threshold ov increasing 1.9 2.0 2.1 v overvoltage hysteresis current ov = 2.15 v 10 12.5 15 a undervoltage threshold uv increasing 0.95 1.0 1.05 v undervoltage hysteresis ? 25 75 125 mv soft ? start (ss) charge current ss = 2.0 v 40 50 70 a discharge current ss = 2.0 v 4.0 5.0 7.0 a charge voltage ? 2.8 3.0 3.4 v discharge voltage ? 0.25 0.3 0.35 v soft ? start clamp offset ff = 1.25 v 1.15 1.25 1.35 v soft ? start fault voltage ov = 2.15 v or lv = 0.85 v ? 0.1 0.2 v blanking blanking time ? 50 150 250 ns ss blanking disable threshold v fb < 1.0 2.8 3.0 3.3 v comp blanking disable threshold v fb < 1.0, ss > 3.0 v 2.8 3.0 3.3 v thermal shutdown thermal shutdown note 3 125 150 180 c thermal hysteresis note 3 5.0 10 15 c 3. guaranteed by design, not 100% tested in production.
ncp1294 http://onsemi.com 6 package pin description package pin # pin symbol function 1 gate external power switch driver with 1.0 a peak capability. rail to rail output occurs when the capacitive load is between 470 pf and 10 nf. 2 i sense current sense comparator input. 3 sync bidirectional synchronization. locks to highest frequency. 4 ff pwm ramp. 5 uv undervoltage protection monitor. 6 ov overvoltage protection monitor. 7 r t c t timing resistor r t and capacitor c t determine oscillator frequency and maximum duty cycle, d max . 8 i set voltage at this pin sets pulse ? by ? pulse overcurrent threshold. 9 v fb feedback voltage input. connected to the error amplifier inverting input. 10 comp error amplifier output. 11 ss charging external capacitor restricts error amplifier output voltage during the power up or fault conditions. 12 lgnd logic ground. 13 v ref 3.3 v reference voltage output. decoupling capacitor can be selected from 0.01 f to 10 f. 14 v cc logic supply voltage. 15 pgnd output power stage ground. 16 v c output power stage supply voltage.
ncp1294 http://onsemi.com 7 v cc + ? + ? ? + v ref = 3.3 v uv lockout start/stop uvl enable v ref ok 3.1 v 3.3 v thermal shutdown 2.0 ma (maximum load current) low sat gate driver 13.5 v s r q q g1 osc g2 + ? v bg (1.263 v) eamp ? + 3.0 v 2.0 v to 1.0 v trip points + ? max duty cycle (sat sense) + ? pwm comp soft ? start clamp ss to 1.8 v max ff discharge g3 + ? 150 ns blank disable i lim ? + max ss det (sat sense) v ref 50 a g4 3.0 v + ? latching discharge ? + 1.0 v 2.0 v ov monitor uv monitor 5.0 a v ref v c gate pgnd lgnd ss ov uv sync r t c t v fb comp ff i sense i set v o off on figure 2. block diagram
ncp1294 http://onsemi.com 8 application information theory of operation feed forward voltage mode control in conventional voltage mode control, the ramp signal has fixed rising and falling slope. the feedback signal is derived solely from the output voltage. consequently, voltage mode control has inferior line regulation and audio susceptibility. feed forward voltage mode control derives the ramp signal from the input line, as shown in figure 3. therefore, the ramp of the slope varies with the input voltage. at the start of each switch cycle, the capacitor connected to the ff pin is charged through a resistor connected to the input voltage. meanwhile, the gate output is turned on to drive an external power switching device. when the ff pin voltage reaches the error amplifier output v comp , the pwm comparator turns off the gate, which in turn opens the external switch. simultaneously, the ff capacitor is quickly discharged to 0.3 v. overall, the dynamics of the duty cycle are controlled by both input and output voltages. as illustrated in figure 4, with a fixed input voltage the output voltage is regulated solely by the error amplifier. for example, an elevated output voltage reduces v comp which in turn causes duty cycle to decrease. however, if the input voltage varies, the slope of the ramp signal will react immediately which provides a much improved line transient response. as an example shown in figure 5, when the input voltage goes up, the rising edge of the ramp signal increases which reduces duty cycle to counteract the change. + ? v in ? + v out power stage r latch & driver gate pwm feedback network ff c comp error amplifier fb figure 3. feed forward voltage mode control the feed forward feature can also be employed to provide a volt ? second clamp, which limits the maximum product of input voltage and turn on time. this clamp is used in circuits, such as forward and flyback converter, to prevent the transformer from saturating. calculations used in the design of the volt ? second clamp are presented in the design guidelines section. figure 4. pulse width modulated by output current with constant input voltage v out v comp ff v in r t c t gate figure 5. pulse width modulated by input voltage with constant output current v in v comp ff i out r t c t gate powering the ic & uvl the undervoltage lockout (uvl) comparator has two voltage references; the start and stop thresholds. during power ? up, the uvl comparator disables v ref (which in ? turn disables the entire ic) until the controller reaches its v cc start threshold. during power ? down, the uvl comparator allows the controller to operate until the v cc stop t hreshold is reached. the ncp1294 requires only 50 a during startup. the output stage is held at a low impedance state in lock out mode. during power up and fault conditions, the soft ? start clamps the comp pin voltage and limits the duty cycle. the power up transition tends to generate temporary duty cycles much greater than the steady state value due to the low output voltage. consequently, excessive current stresses often take place in the system. soft ? start technique alleviates this problem by gradually releasing the clamp on the duty cycle to eliminate the in ? rush current. the duration
ncp1294 http://onsemi.com 9 of the soft ? start can be programmed through a capacitance connected to the ss pin. the constant charging current to the ss pin is 50 a (typ). the v ref (ok) comparator monitors the 3.3 v v ref output and latches a fault condition if v ref falls below 3.1 v. the fault condition may also be triggered when the ov pin voltage rises above 2.0 v or the uv pin voltage falls below 1.0 v. the undervoltage comparator has a built ? in hysteresis of 75 mv (typ). the hysteresis for the ov comparator is programmable through a resistor connected to the ov pin. when an ov condition is detected, the overvoltage hysteresis current of 12.5 a (typ) is sourced from the pin. in figure 6, the fault condition is triggered by pulling the uv pin to the ground. immediately, the ss capacitor is discharged with 5.0 a of current (typ) and the ga te output is disabled until the ss voltage reaches the discharge voltage of 0.3 v (typ). the ic starts the soft ? start transition again if the fault condition has recovered as shown in figure 6. however, if the fault condition persists, the ss voltage will stay at 0.1 v until the removal of the fault condition. figure 6. the fault condition is triggered when the uv pin voltage falls below 1.0 v. the soft ? start capacitor is discharged and the gate output is disabled. ch2: envelop of gate output, ch3: ss pin with 0.01 f capacitor, ch4: uv pin current sense and overcurrent protection the current can be monitored by the i sense pin to achieve pulse by pulse current limit. various techniques, such as a using current sense resistor or current transformer, can be adopted to derive current signals. the voltage of the i set pin sets the threshold for maximum current. as shown in figure 7, when the i sense pin voltage exceeds the i set voltage, the current limit comparator will reset the gate latch flip ? flop to terminate the gate pulse. figure 7. the gate output is terminated when the i sense pin voltage reaches the threshold set by the i set pin. ch2: i sense pin, ch4: i set pin, ch3: gate pin the current sense signal is prone to leading edge spikes caused by the switching transition. a rc low ? pass filter is usually applied to the current signals to avoid premature triggering. however, the low pass filter will inevitably change the shape of the current pulse and also add cost. the ncp1294 uses leading edge blanking circuitry that blocks out the first 150 ns (typ) of each current pulse. this removes the leading edge spikes without altering the current waveform. the blanking is disabled during soft ? start and when the v comp is saturated high so that the minimum on ? time of the controller does not have the additional blanking period. the max ss detect comparator keeps the blanking function disabled until ss charges fully. the output of the max duty cycle detector goes high when the error amplifier output gets saturated high, indicating that the output voltage has fallen well below its regulation point and the power supply may be underload stress. oscillator and synchronization the switching frequency is programmable through a rc network connected to the r t c t pin. as shown in figure 8, when the r t c t pin reaches 2.0 v, the capacitor is discharged by a 1.0 ma current source and the gate signal is disabled. when the r t c t pin decreases to 1.0 v, the gate output is turned on and the discharge current is removed to let the r t c t pin ramp up. this begins a new switching cycle. the c t charging time over the switch period sets the maximum duty cycle clamp which is programmable through the r t value as shown in the design guidelines. at the beginning of each switching cycle, the sync pin generates a 2.5 v, 320 ns (typ) pulse. this pulse can be utilized to synchronize other power supplies.
ncp1294 http://onsemi.com 10 figure 8. the sync pin generates a sync pulse at the beginning of each switching cycle. ch2: gate pin, ch3: r t c t , ch4: sync pin figure 9. operation with external sync. ch2: sync pin, ch3: gate pin, ch4: r t c t pin an external pulse signal can feed to the bidirectional sync pin to synchronize the switch frequency. for reliable operation, the sync frequency should be approximately 20% higher than free running ic frequency. as show in figure 9, when the sync pin is triggered by an incoming signal, the ic immediately discharges c t . the gate signal is turned on once the r t c t pin reaches the valley voltage. because of the steep falling edge, this valley voltage falls below the regular 1.0 v threshold. however, the r t c t pin voltage is then quickly raised by a clamp. when the r t c t pin reaches the 0.95 v (typ) valley clamp voltage, the clamp is disconnected after a brief delay and c t is charged through r t . design guidelines switch frequency and maximum duty cycle calculations oscillator timing capacitor, c t , is charged by v ref through r t and discharged by an internal current source. during the discharge time, the internal clock signal sets the gate output to the low state, thus providing a user selectable maximum duty cycle clamp. charge and discharge times are determined by following general formulas; t c r t c t ln (v ref v valley ) (v ref v peak ) t d r t c t ln (v ref v peak i d r t ) (v ref v valley i d r t ) where: t c = charging time; t d = discharging time; v valley = valley voltage of the oscillator; v peak = peak voltage of the oscillator. substituting in typical values for the parameters in the above formulas, v ref = 3.3 v, v valley = 1.0 v, v peak = 2.0 v, i d = 1.0 ma: t c 0.57r t c t t d r t c t ln 1.3 0.001r t 2.3 0.001r t d max 0.57 0.57 in 1.3 0.001r t 2.3 0.001r t it is noticed from the equation that for the oscillator to function properly, r t has to be greater than 2.3 k. select rc for feed forward ramp if the line voltage is much greater than the ff pin peak voltage, the charge current can be treated as a constant and is equal to v in /r. therefore, the volt ? second value is determined by: v in t on (v comp v ff(d) ) r c where: v comp = comp pin voltage; v ff(d) = ff pin discharge voltage. as shown in the equation, the volt ? second clamp is set by the v comp clamp voltage which is equal to 1.8 v. in forward or flyback circuits, the volt ? second clamp value is designed to prevent transformers from saturation. in a buck or forward converter, volt ? second is equal to v in t on v out t s n n = transformer turns ratio, which is a constant determined by the regulated output voltage, switching period and transformer turns ration (use 1.0 for buck converter). it is interesting to notice from the aforementioned two equations
ncp1294 http://onsemi.com 11 0.0001 0.001 0.01 c t ( f) 0 800 frequency (khz) 400 700 600 500 300 200 100 1000 10000 1000000 r t ( ) 0.50 1.00 duty cycle (%) 0.80 0.95 0.90 0.85 0.75 0.70 0.65 0.60 0.55 100000 figure 10. typical performance characteristics, oscillator frequency vs. c t figure 11. typical performance characteristics, oscillator duty cycle vs. r t r t = 5.0 k r t = 10 k r t = 50 k that during steady state, v comp doesn?t change for input voltage variations. this intuitively explains why ff voltage mode control has superior line regulation and line transient response. knowing the nominal value of v in and t on , one can also select the value of rc to place v comp at the center of its dynamic range. select feedback voltage divider as shown in figure 12, the voltage divider output feeds to the fb pin, which connects to the inverting input of the error amplifier. the non ? inverting input of the error amplifier is connected to a 1.27 v (typ) reference voltage. the fb pin has an input current which has to be considered for accurate dc outputs. the following equation can be used to calculate the r1 and r2 value r2 r1 r2 v out 1.27 where ? is the correction factor due to the existence of the fb pin input current ier. (ri r1 r2)ier ri = dc resistance between the fb pin and the voltage divider output. ier = v fb input current, 1.3 a typical. design voltage dividers for ov and uv detection in figure 13, the voltage divider uses three resistors in series to set ov and uv threshold seen from the input voltage. the values of the resistors can be calculated from the following three equations, where the third equation is derived from ov hysteresis requirement. v in(low) r2 r3 r2 r3 r1 1.0 v (a) v in(high) r3 r2 r3 r1 2.0 v (b) 12.5 a (r1 r2) v hyst (c) where: v in(low) , v in(high) = input voltage ov and uv threshold; v hyst = ov hysteresis seen at v in it is self ? evident from equation a and b that to use this design, v in(high) has to be two times greater than v in(low) . otherwise, two voltage dividers have to be used to program ov and uv separately. figure 12. the design of feedback voltage divider has to consider the error amplifier input current + ? ? + v out r1 comp fb r2 ri 1.27 ier figure 13. ov/uv monitor divider v in r1 r2 r3 v uv v ov
ncp1294 http://onsemi.com 12 package dimensions soic ? 16 d suffix case 751b ? 05 issue k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 18 16 9 seating plane f j m r x 45 g 8 pl p ? b ? ? a ? m 0.25 (0.010) b s ? t ? d k c 16 pl s b m 0.25 (0.010) a s t dim min max min max inches millimeters a 9.80 10.00 0.386 0.393 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019 6.40 16x 0.58 16x 1.12 1.27 dimensions: millimeters 1 pitch soldering footprint 16 89 8x package thermal data parameter soic ? 16 unit r jc typical 28 c/w r ja typical 115 c/w
ncp1294 http://onsemi.com 13 package dimensions ??? ??? 4.90 5.10 0.193 0.200 b 4.30 4.50 0.169 0.177 c ??? 1.20 ??? 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.18 0.28 0.007 0.011 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash. protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane ? w ? . section n ? n seating plane ident. pin 1 1 8 16 9 detail e j j1 b c d a k k1 h g ? u ? s u 0.15 (0.006) t s u 0.15 (0.006) t s u m 0.10 (0.004) v s t 0.10 (0.004) ? t ? ? v ? ? w ? 0.25 (0.010) 16x ref k n n tssop ? 16 case 948f ? 01 issue b 7.06 16x 0.36 16x 1.26 0.65 dimensions: millimeters 1 pitch soldering footprint on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. ncp1294d publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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